1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices such as ICs (integrated circuits), MOSFETs (MOS field effect transistors), and IGBTs (insulated gate bipolar transistors).
2. Description of the Related Art
In recent years, computers and communication equipment have frequently used, in their essential parts, integrated circuits (ICs) in which a plurality of transistors, resistors and the like are combined to construct an electronic circuit and integrated on one chip. An IC containing a power semiconductor element is called a power IC.
An IGBT is a power element composed in one chip exhibiting the high speed switching and voltage driving characteristics of a MOSFET and the low ON voltage characteristic of a bipolar transistor. Applications of IGBTs are expanding to industry fields including general purpose invertors, AC servo devices, uninterrupted power supplies (UPSs), switching power supplies and the like, as well as household appliances including microwave ovens, rice cookers, strobes and the like.
Development efforts are advancing towards next generation devices using new chip structures and exhibiting a low ON voltage to achieve low power consumption and high efficiency in apparatuses that employ them.
Structures of IGBTs include a punch-through (PT) type, a non-punch through (NPT) type, and a field stop (FS) type. Almost all the IGBTs that are presently mass-produced have an n-channel vertical double diffusion structure, except in some audio power amplifiers, which use a p-channel type element. The present specification also describes n-channel IGBTs.
The PT type comprises an n+ layer (an n buffer layer) between a p+ type epitaxial substrate and an n− layer (an n type active layer), and an depletion layer in the n type active layer reaches the n buffer layer. The PT type is a basic structure in the mainstream of IGBTs. In a system of breakdown voltage of 600 V, for example, though a thickness of 70 μm is sufficient for the active layer, a total thickness including the p+ type substrate amounts to 200 μm to 300 μm. Accordingly, NPT type IGBTs employing a shallow p+ collector layer with a low dose amount and the FS type IGBTs having a field stop layer are being developed using a FZ (floating zone) substrate without using an epitaxial substrate in order to obtain a low cost chip.
FIG. 13 is a sectional view of an NPT type IGBT. The NPT type, which does not use a p+ substrate, has a substantially reduced total thickness of a substrate 51 as compared with the PT type, which uses an epitaxial substrate. This structure allows control of a hole injection rate, thereby achieving high speed switching without life time control, although ON voltage may be rather high depending on a thickness and resistivity of the n-type active layer 51a. Chip cost reduction is, however, possible owing to the use of an FZ substrate 51 without using a p+ epitaxial substrate as described above. In FIG. 13, the reference numeral 52 represents a p type base layer; 53, an n-type emitter layer; 54, a gate oxide film; 55, a gate electrode; 56, an interlayer dielectric film; 57, a front surface electrode that is an emitter electrode; 62, a p type collector layer; and the reference numeral 63 represents a rear surface electrode that is a collector electrode.
FIG. 14 is a sectional view of an FS type IGBT. The FS type IGBT has basically the same structure as of the PT type IGBT. The FS type IGBT uses an FZ substrate 51 without using a p+ epitaxial substrate and has a total thickness of the substrate 51 of 100 μm to 200 μm. The n-type active layer 51a has a thickness of about 70 μm corresponding to a breakdown voltage of 600 V as in the case of the PT type, and is depleted. Accordingly, an n type layer, being an n type field stop (FS) layer 61, is provided under the n-type active layer 51a. In the collector side, a shallow p+ diffusion layer is used for a low injection dose collector that is a p-type collector layer 62. This structure does not need lifetime control as in the case of the NPT type. In addition, a structure combining this FS type IGBT with a trench IGBT structure (not shown in the figure) is known, and intended to provide further reduction of ON voltage, in which a narrow and deep groove is formed from the chip front surface and a MOSFET structure is formed on the side surface of the trench. Reduction of the total thickness is in progress recently by means of design optimization.
In recent years, matrix converters that directly perform AC to AC conversion without intermediate DC are drawing attention. The matrix converter does not need a capacitor, which is different from conventional inverters, and has an advantage of decreasing higher harmonics in a power supply. However, since the input is AC, a reverse withstand voltage capability is required for semiconductor switches in the matrix converter. If a conventional IGBT is used, a series-connected diode is required for blocking a reverse voltage. A reverse-blocking IGBT, as shown in FIG. 15, has reverse blocking ability following basic characteristics of a conventional IGBT. The basic structure is the same as that of the NPT type IGBT except that an isolation layer is formed in the reverse-blocking IGBT. A reverse-blocking IGBT, owing to elimination of a series-connected diode, reduces a conduction loss to about a half, contributing considerable enhancement of a conversion efficiency of a matrix converter. High performance reverse blocking IGBTs have been manufactured by combining the technologies of forming a deep junction (formation of a p type isolation layer) of about 100 μm or more and of manufacturing a very thin wafer of about 100 μm thick or less. In FIG. 15, the reference numeral 70 represents a passivation film.
For achieving a thin IGBT with a thickness of about 70 μm, there are many technological problems in the manufacturing process, including the occurrence of warping, which may arise due to rear surface back-grinding, ion injection from the rear surface, and rear surface heat treatment required in the manufacturing process. The manufacturing process will be described for an FS type IGBT as follows.
FIGS. 16 through 20, showing a method of manufacturing a conventional semiconductor device, are sectional views of essential parts of the semiconductor device illustrated in a sequence of the manufacturing process. The semiconductor device is an FS type IGBT in the following description.    (1) A gate oxide film 54 (SiO2) and a gate electrode 55 of polycrystalline silicon (poly-Si) are deposited on an FZ-N substrate 51 and worked. On the surface of the gate electrode 55, an interlayer dielectric film 56 (BPSG in this example) is deposited and worked to produce an insulated gate structure.    (2) A p base layer 52 (p+) is formed in the surface region of the FZ-N substrate 51 and then, an n-type emitter layer 53 is formed in the p base layer 52.    (3) A front surface electrode 57 that is an emitter electrode composed of aluminum-silicon film in contact with the n-type emitter layer 53. The aluminum-silicon film is then heat treated at a relatively low temperature of 400° C. to 500° C. in order to achieve a stable joint performance and low resistance wiring. Though not depicted, an insulating protection film of a polyimide film is formed covering the front surface.
A process in the front surface side has been completed up to this step as shown in FIG. 16.    (4) The FZ-N substrate 51 is made thin by means of back grinding, etching or other technique from the rear surface 58 down to a desired thickness as shown in FIG. 17.    (5) Then, as shown in FIG. 18, ion injection is conducted from the rear surface 58 to form ion injection layers 59 and 60 for forming an n type layer that is a field stop (FS) layer 61 and a high concentration p type collector layer 62 (p+ layer), respectively (these two layers are indicated in FIG. 19). In some cases, a p layer of BF2 is injected as a contact layer onto the rear surfaced 58 to obtain a high concentration layer after boron ion injection in order to establish ohmic contact with a rear surface electrode 63 that is a collector electrode.    (6) Heat treatment for annealing is conducted using an electric furnace (not illustrated in the figures). The heat treatment temperature is a relatively low temperature in the range of 350° C. to 500° C. In this step, a field stop layer (an FS layer) 61 (an n layer) and a p type collector layer 62 (a p+ layer) are formed as shown in FIG. 19.    (7) After that, a rear surface electrode 63 is formed in combination of metal films selected from an aluminum layer, a titanium layer, a nickel layer, a gold layer and the like on the high concentration p type collector layer 62 (a p+ layer) as shown in FIG. 20.    (8) Though not illustrated, after dicing into chips, aluminum wires are fixed onto the surface of the front surface electrode 57 using an ultrasonic wire bonding apparatus. The rear surface electrode 63 is joined onto a base through a solder layer. Thus, an FS type IGBT is completed.
There are several methods in the annealing step (6) that use laser annealing that allows heating solely in the surface region for activating the ion injected layer.
Japanese Unexamined Patent Application Publication No. 2003-059856 discloses use of YAG 3ω and YAG 2ω laser for activating the n layer.
Japanese Patent No. 4043865 discloses use of two laser apparatus for activating an ion injected layer.
Japanese Unexamined Patent Application Publication No. 2005-223301 discloses a method to activate an impurity layer using two laser irradiation apparatus that irradiate with pulse laser and form wide pulses.
Japanese Patent No. 4088011 discloses an activation rate of impurities in a rear surface region of an FS IGBT.
Japanese Unexamined Patent Application Publication No. 2009-032858 discloses a laser irradiation apparatus comprising a first light source and a second light source that emit laser pulses with different wavelengths, and an optical system that irradiates an work piece with an overlap between irradiated areas.
Japanese Unexamined Patent Application Publication No. 2008-270243 discloses use of two laser oscillators (laser light emission devices), and irradiation by a wide pulse laser formed from a former pulse and a latter pulse that is emitted after an inserted delayed time.
Some problems in the above-described conventional examples are described below.    1) Despite intending full activation down to the FS layer 61 (an n layer) of an FS type IGBT, it is impossible to accomplish satisfactory activation with the heat treatment at a relatively low temperature of 350° C. to 500° C. using an electric furnace.    2) Even if the pulse width is elongated or the repeating frequency is increased as described above, when an interruption exists in the laser light irradiation, the temperature in the heated place decreases during the interruption period. As a result, as shown in FIG. 21, heat is not conducted sufficiently to a deep FS layer 61 (an n layer) at about 2 μm from the surface, which causes an unstable concentration profile and insufficient recovery of defects in the FS layer. Therefore, satisfactory activation cannot be achieved.    (3) Laser irradiation undesirably affects the front surface side when conducted only from the rear surface 58 side by conventional methods. For example, the laser irradiation process may raise the temperature of the functional structure on the front surface side and fuse the front surface electrode 57.    (4) The output power of an ordinary continuous wave (CW) laser is very much lower than that of a normal pulse laser. Consequently, sufficient activation is impossible. A short pulse laser, on the other hand, though it delivers output power with a high energy density, cannot activate an ion injection layer 59 (to become an FS layer) at a deep position from the rear surface 58 as shown in FIG. 21, and further, cannot fully recover the lattice defects.    (5) Irradiation of a high energy density laser causes a surface profile to be a box profile, resulting in variation of depth of diffusion layers, which are a p type collector layer 62 and an FS layer 61.    (6) Japanese Patent No. 4043865, Japanese Unexamined Patent Application Publication No. 2009-032858, and Japanese Unexamined Patent Application Publication No. 2008-270243, as referred to above, disclose that two laser light pulses are used to obtain a wide pulse that is emitted for annealing. However, these documents do not disclose such a method of manufacturing a semiconductor device using a plurality of laser light pulses to form laser light with a substantially CW waveform, and performing annealing of the ion injection layer by irradiation of the substantially CW laser light.